Typical stand alone memories are used in coordination with a micro processor, an ASIC circuit or some other type of control circuit. In these applications the stand alone memories coupled to the controller, or master, by way of a bi-directional data bus. In order to affect a read or write to the stand alone memory the master must send an enable signal to the memory. This handshaking of master and memory wastes valuable time on the data bus and typically requires at least one extra or dead cycle.
As applications and processing become faster and bus allocation becomes more critical it is necessary to reduce the number of handshaking cycles required and thus increase the efficiency of the memory in a data processing system. To this end several memories have been developed which require no enable signal or handshaking with the master. The memory becomes its own master determining when to provide and receive data and information from the data bus. One such memory initiates the data transfer to and from the itself. The data interface between the master and the memory is bi-directional (i.e. a common input/output). Here the memory and not the master determines when to release the bus and allow the master to drive data into the memory device. Likewise the memory determines when to start driving data out of the memory. The memory protocol allows data to be driven by the master and by the memory in a single clock cycle, however, not concurrently.
A problem arises as various ASIC technologies are used over a wide variety of clock speeds. There is also a significant number of types of masters operating at a large variety of clock speeds. This means that the memory is required to operate at over a large range of possible operating frequencies and under various operating conditions, such as over temperature. It is difficult to process one product that can operate over such a large range of frequencies while maintaining consistency and process yields. It is desirable to have one part that is applicable to several applications which will allow the memory to adjust an output delay based on the input frequency.